Vendor: Aragio Solutions Category: GPIO

I3C I/O Library

The I3C library provides a bi-directional I/O driver designed for the I3C two-line interface.

Contact Provider Request Datasheet

Overview

The I3C library provides a bi-directional I/O driver designed for the I3C two-line interface. It is compliant with the MIPI Specification for I3C –Version 1.1, 27 Novenber 2019.
The design supports the IC3 push-pull and open-drain modes as well as legacy Fm and Fm+ open-drain modes at the bus operating voltages of 1.2V and 1.8V.
This 5nm library is available in an inline flip chip implementation.
To design a functional I/O power domain with this cell, an additional library is required – 1.8V Support: Power. That library contains isolated analog I/O, and a full complement of power cells along with spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while

Key features

  • Supported I3C operating modes:
    • I3C push-pull mode – up to 12.5 MHz
    • I3C open-drain mode – up to 12.5 Mbps data rate
    • Legacy Fast mode (Fm) – up to 400 Kbps data rate
    • Legacy Fast mode (Fm+) – up to 1.0 Mbps data rate
    • Output enable and mode select
    • Receiver enable
    • Standard LVCMOS compatible input with optional Schmitt trigger (hysteresis)
    • ESD protection is accomplished with stacked NMOS breakdown devices
    • Power-on sequencing independent design with Power-On Control
    • DVDD = 1.2V or 1.8V
    • Pad VDDP (open-drain) = 1.65V to 1.95V or 1.20V to 1.30V – independent of DVDD
    • The circuit consumes no DC supply current in the static state in the open-drain modes
    • Fault-tolerant to 1.98V at PAD (no current flow when DVDD = 0V)
  • In open-drain modes, this cell requires a pull-up to a high voltage power supply (VDDP). The sizing of an external resistor or appropriate pull-up network is application dependent.

What’s Included?

  • Physical abstract in LEF format (.lef)
  • Timing models in Synopsys Liberty formats (.lib and .db)
  • Calibre compatible LVS netlist in CDL format (.cdl)
  • GDSII stream (.gds)
  • Behavioral Verilog (.v)
  • Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • Databook (.pdf)
  • Library User Guide - ESD Guidelines (.pdf)

Specifications

Identity

Part Number
RGO_TSMC05_15V18_N5_45F_I3C
Vendor
Aragio Solutions
Type
Silicon IP

Provider

Contact Aragio Solutions

Learn more about GPIO IP core

GPIO Solutions for CERN’s Radiation-Hardened Applications

For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.

A Generic Solution to GPIO verification

This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.

How AI and Edge Computing Are Accelerating RISC-V Adoption

One of the critical problems in today’s computing is that transporting data can be more costly in energy and time than computing. With the growing complexity of AI models, SoC designers have shifted their focus toward optimizing memory hierarchies, increasing bandwidth in interconnects, and architecting based on workloads for improved efficiency.

Ensuring reliability in Advanced IC design

To complete our task as engineers we rely on the tools we use. We collaborated with Siemens EDA solutions back in 2025 on a webinar about how we use their tools to develop our designs and layouts.

Integrating Post-Quantum Cryptography (PQC) on Arty-Z7

Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?

Frequently asked questions about GPIO Pad Library IP cores

What is I3C I/O Library?

I3C I/O Library is a GPIO IP core from Aragio Solutions listed on Semi IP Hub.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP