1.2V GPIO library designed for the SVID three-line interface.

The 1.2V GPIO library provides an open-drain bi-directional I/O driver designed for the SVID three-line interface. It is compliant with the Intel SVID specification.
This 5nm library is available in an inline flip chip implementation.
To design a functional I/O power domain with this cell, an additional library is required – 1.8V Support: Power. That library contains isolated analog I/O, and a full complement of power cells along with spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.

• Open drain operation only
  • 24mA rated sink current @ 1.2V
• Operating frequency – up to 25MHz
• Fault-tolerant to 1.32V at PAD (no current flow when DVDD = 0V)
• Output enable
• Receiver enable
• Standard LVCMOS compatible input with Schmitt trigger (hysteresis)
• Power-on sequencing independent design with Power-On Control
• DVDD = 1.08V to 1.32V
• Pad VDDP = 0.95V to 1.08V – independent of DVDD
• The circuit consumes no DC supply current in the static state
• A pull-down function is provided to prevent the PAD port from floating when an open-drain configuration is not used on the system board.

• Physical abstract in LEF format (.lef)
• Timing models in Synopsys Liberty formats (.lib and .db)
• Calibre compatible LVS netlist in CDL format (.cdl)
• GDSII stream (.gds)
• Behavioral Verilog (.v)
• Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
• Databook (.pdf)
• Library User Guide - ESD Guidelines (.pdf)