1.2V Low Voltage Detector (LVD), Fujitsu 90nm
The AR22F01 is a mass-production proven low voltage detector (LVD) IP.
- Voltage Monitor
- Mass Production
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
1.2V Low Voltage Detector (LVD), Fujitsu 90nm
The AR22F01 is a mass-production proven low voltage detector (LVD) IP.
Cap-less 100mA Low Noise LDO, XFAB 250nm
The LDO is capable of outputting 1.2V voltage with maximum power of 100mA and low drop out voltage of less than 200mV.
Cap-less 25mA Low Noise LDO, Fujitsu 90nm
The AR25F01 is a mass-production proven cap-less LDO IP.
Multi-2 Descrambler Supporting BCAS for ISDB-T,TMM in Japan
MEGACAST MULTI2 IP core implements the MULTI2 encryption/decryption algorithms as specified by ISO9979/0009 algorithm register en…
USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.
SATA 1-to-1 Speed Bridge with Sandbox
The IntelliProp SATA 1-to-1 Speed Bridge with Sandbox (IPP-SA110A-BR) design provides SATA compliant connections to a SATA host a…
The IntelliProp IPC-SS107A-DT SAS Target Core is an industry standard Serial-SCSI (SAS) Core that enables device applications to …
This is a pipelined high throughput AES core capable of starting a new encryption every clock cycle.
16-Bit Sigma-Delta ADC with 10 Input Channels, XFAB 0.25um
The AR32X3A specifies a silicon proven, very low power sigma-delta ADC for high-precision measurement system.
The LDS SATA RECORDER XV6 IP is a recorder system IP.
64 State 4x8PSK (4D 8PSK) CCSDS ECSS Viterbi Decoder
The VA06C is a fully parallel 64 state error control decoder using the maximum likelihood Viterbi algorithm for the 4x8PSK (4D 8P…
Our FPGA core is optimized and 80% SMALLER THAN THE COMPETITION!
10Gbps Low Latency Ethernet Solution
The 10Gbps 32-bit Ethernet IP solution offers a fully integrated IEEE802.3-2008 (802.3ae) compliant package for NIC (Network Inte…
RSA public key cryptography with APB interface
The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library.
SATA III HOST Controller on Virtex 6
The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 …
High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS
Granite SemicCom's Digital PLL is intended for applications such the Clock-Multiplying-Unit in a SERDES or a Clock-Driver with fr…
DVB-RCS and IEEE 802.16 WiMAX turbo encoder
This is an 8 state DVB-RCS and IEEE 802.16 WiMAX compatible parallel concatenated turbo encoder.
The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2.
Rambus MIPI Testbench from Rambus emulates a MIPI device enabling end-to-end simulation of a MIPI design.