Vendor: EnSilica Category: Symmetric Crypto

High Throughput AES

This is a pipelined high throughput AES core capable of starting a new encryption every clock cycle.

AES View all specifications

Overview

This is a pipelined high throughput AES core capable of starting a new encryption every clock cycle. It is intended for both ASIC and FPGA target technologies. The core supports all key sizes 128, 192 and 256 and the key size can be selected per encryption cycle.

Key features

  • Optimised for both ASIC and FPGA targets
  • Per packet dynamic selection of key size
  • Fully synchronous
  • Verilog RTL
  • Latency of 15 clock cycles
  • New encryption per clock cycle
  • Supports counter mode

Benefits

  • Achieves the highest throughput on both both ASIC ans FPGA targets
  • Fully tested against NIST test suite

What’s Included?

  • RTL source code
  • Testbench
  • Synthesis and STA scripts
  • Comprehensive documentation

Specifications

Identity

Part Number
eSi-AES-HT
Vendor
EnSilica
Type
Silicon IP

Security

Crypto Algorithm
AES

Provider

EnSilica
HQ: UK

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Frequently asked questions about Symmetric Cryptography IP cores

What is High Throughput AES?

High Throughput AES is a Symmetric Crypto IP core from EnSilica listed on Semi IP Hub.

How should engineers evaluate this Symmetric Crypto?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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