The LINFlexD Controller is a serial communication interface designed for Local Interconnect Network (LIN) applications.
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The LINFlexD Controller is a serial communication interface designed for Local Interconnect Network (LIN) applications.
xSPI NOR/NAND Flash & HyperRAM Controller
Emerging high-performance applications demand increasingly fast read throughputs from NOR_Flash/ NAND Flash/ HyperRAM memory devi…
MIPI CSI-2 Receiver v2.0 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels.
JPEG codec is designed to provide high performance solution for jpeg decoder and encoder.
64-bit RISC-V core with out-of-order pipeline based complex for Linux-based embedded systems
64-bit RISC-V core with out-of-order pipeline based complex.
32-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture.
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
The BRIDGE_UART_I2C IP Core provides a simple and convenient way to interface a standard UART bus to a standard I2C bus.
The CryptoManager RT-6xx v3 Root of Trust family from Rambus is the latest generation of fully programmable FIPS 140-3 compliant …
Single 512-bit SIMD DSP for Vision/Radar/Lidar/AI
Built on our latest Xtensa NX architecture and offers up to 2.18TOPS of performance The Cadence® Tensilica® Vision Q7 DSP deliver…
The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA.
The 18-bit Pipeline DSP slice IP Core provides the best utilization of device resources like memory, I/O, processor and clock.
Silicon agnostic Ethernet MAC IP for 10G, 25G speeds Ethernet MAC 10G/25 IP is a solution that enables the host to communicate da…
Ethernet 1G/2.5G/5G/10G/25G and CPRI 7.0 PCS
The vendor offers a PCS IP core that can be used for both Ethernet and CPRI.
Low Power PLL for TSMC 40nm ULP
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is design…
The SPI to AXI Bridge IP core is commonly used as a monitor interface to allow external devices to access the internal AXI bus.
Ultra Compact 32-bit RISC-V CPU Core
AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require…
Ethernet TSN MAC 10M/100M/1G/2.5G
Silicon agnostic Ethernet TSN MAC IP, IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features The TSN MAC 10M/100M…
The DB-SPI-XIP-FLASH-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad…
Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter - GlobalFoundries 55nm
CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Re…