Ultra-Low-Latency 10GE PHY+MAC
Having the lowest network latency is critical for Accelerated Finance.
- Single-Protocol PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Ultra-Low-Latency 10GE PHY+MAC
Having the lowest network latency is critical for Accelerated Finance.
Ultra Low Latency 10G TCP Endpoint
The TCP Endpoint implements a full, reliable streaming network stack in FPGA logic.
10 Gb/s full HW stack UDP/IP Transmitter/Receiver
10 Gb/s full HW stack UDP/IP Transmitter/Receiver IP block for high performance data transfers from embedded Ethernet based syste…
Switching regulator, inductor-based, PWM mode, high efficiency
The eSR-Tugela is an inductor-based buck switching regulator with high efficiency.
Audio CODEC with 100 dB Dynamic Range, 24-bit stereo PWM DAC, six-channel ADC
YANZI-A-hexCOD-MT1-LR-VD.02 is a high-performance audio CODEC with 6 analog-to-digital converters (ADC) ensuring the most precise…
The D/AVE HD 2.5D GPU family is an evolution of the D/AVE 2D family supporting high quality 2D and 3D rendering for displays up t…
D/AVE 3D is cost-efficient IP core for 3D graphics applications.
3.3V I/O Library with I2C compliant ODIO IN GF 65/55nm
A 3.3V wire-bond I/O library, a 1.2V ODIO and 5V tolerant ODIO.
1.8V GPIO, 1.8V & 3.3V Analog in TSMC 180nm BCD
A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with associated ESD cells.
Wirebond I/O Library in TSMC 130nm
A radiation-hardened TSMC 130nm Wirebond I/O Library with 3.3V GPIO, 3.3V LVDS TX & RX, 3.3V I2C ODIO, 3.3V Analog cell, OTP cell…
2.5V GPIO with 2Gbps LVDS RX TX and Analog Cell in GlobalFoundries 65nm LPe
A GlobalFoundries 65nm LPE Wirebond I/O library with 2.5V GPIO, 2Gbps LVDS TX RX and 2.5V Analog/RF cell with associated ESD.
Image Signal Processor (5MP, 2X Sensors) IP
This is a versatile system-on-chip device designed for automotive, security and a multitude of other camera applications.
I3C Controller IP- Slave, Parameterized FIFO, APB Bus
The DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
I3C Controller IP – Master, Parameterized FIFO, APB Bus
The DB-I3C-M-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
embedded-USB2 (eUSB2) Repeater
CT20603 IP implements a dual-role capable eUSB2 repeater enabling an eUSB2 PHY in SOCs to support connections with USB2.0 complia…
16 state DVB-RCS2 Turbo Encoder
This is a 16 state DVB-RCS2 compatible parallel concatenated turbo encoder.
Time Synchronization over Internet Protocol
The ST 2059 core is an FPGA IP core that generates timing and clock signals according to the SMPTE ST 2059 standard defined by th…
The TRC16024CPA is a four lane Gen 1,2,3,4 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transm…
Entry-level network-on-chip (NoC) IP for low power and cost efficiency.
USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
Our company offers a configurable and adaptable USB 2.0 OTG controller IP core, suitable for a wide range of applications.