What is xSPI NOR/NAND Flash & HyperRAM Controller?
xSPI NOR/NAND Flash & HyperRAM Controller is a SPI / QSPI XSPI IP core from Mobiveil Inc. listed on Semi IP Hub.
Emerging high-performance applications demand increasingly fast read throughputs from NOR_Flash/ NAND Flash/ HyperRAM memory devi…
Emerging high-performance applications demand increasingly fast read throughputs from NOR_Flash/ NAND Flash/ HyperRAM memory devices As new age lower-end microcontrollers (MCUs) continue to shrink in die size, their internal memory is very limited. They need a low pin count, high-performance memory subsystem. Similarly, there are consumer applications that are space-constrained and require instant-on, such as digital still cameras, DSLRs and home automation. So, OEMs are looking for simple, flexible, high performance and low-energy memory solutions with backward compatibility to meet their needs. The major NOR Flash memory device vendors responded with such devices by expanding from current Quad I/O to OctaFlash Memory (8 I/O) resulted in substantial increase in Serial NOR Flash throughput.
For example, the new-generation OctaFlash by Macronix is built on Serial Peripheral Interface (SPI) and command set, providing extendable I/O capability(x8). The data transfer rate has been increased from 100MB/s of Quad I/O Serial NOR Flash to 400MB/s, claims Macronix.
This resulted in lower-density memory subsystem interfaces trending toward x4/x8 SPI (xSPI) interfaces and performance growing exponentially. Mobiveil’s approach on this emerging scenario results in adapting to JEDEC xSPI compliant NOR Flash/ NAND Flash controller supporting devices from various vendors. The IP can function as simple ‘SPI Flash Controller’ or, ‘Quad-SPI Flash Controller or Octa- SPI Flash Controller’ or ‘Dual QSPI Controller’, thus compatible with legacy devices also. The controller architecture is SoC friendly and supports multiple chip-selects.
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xSPI NOR/NAND Flash & HyperRAM Controller is a SPI / QSPI XSPI IP core from Mobiveil Inc. listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
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