Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes
TRC3104SBA is a Quad SerDes transceiver device, capable of transmitting 1.06 to 3.125Gb/s signals over Backplane, Fiber Channel, …
- TSMC
- 180nm
- BCDG2
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes
TRC3104SBA is a Quad SerDes transceiver device, capable of transmitting 1.06 to 3.125Gb/s signals over Backplane, Fiber Channel, …
This high performance, fully programmable Reed Solomon Decoder IP Core is intended for use in a wide range of applications requir…
USB 2.0 On-The-Go IP Core, Compliance Certified
A ‘Dual-Role’ USB 2.0 On-The-Go IP Core that operates as both an USB 2.0 peripheral or as an USB 2.0 OTG host in a point-to-point…
SONET/SDH OC-12 Transceiver/CDR
The SMS2012 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration…
Universal Asynchronous Receiver/Transmitter Module
The UARTmodule is part of Inicore's IPmodule family.
Serial Peripheral Interface (SPI) Master Module
The SPIMmodule is part of Inicore's IPmodule family.
CAN Controller Core with 8/16 Message Objects
CANmodule-III is a full functional CAN controller module that supports the concept of mailboxes.
This core is a fully compliant implementation of the Message Digest Algorithm MD5.
Helion offer a suite of AES-GCM solutions which allow the user to choose a level of hardware acceleration which closely fits the …
This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1.
This core family implements various aspects of the AES ( Encryption Standard) algorithm.
Infiniband 4X Link Protocol Engine
The Link Protocol Engine (LPE) is single core solution incorporating in Link Layer of Open System Interconnect (OSI) which signif…
The Gigabit Ethernet Media Access Controller is integrated Gigabit Ethernet MAC solution for Gigabit applications.
Inter-Integrated Circuit (I2C) Master Module
The Inter-IC bus, or I2C bus is a two wire serial bus.
The iniADPLL is an all digital implementation of a phase locked loop.
Universal G704-E1 Framer / Deframer Core
The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier.
High-Level Data Link Controller
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Tra…
6809 compatible 8-bit microprocessor
iniCPU, a 8-bit micro processor, enables embedded computing and controlling on chip.
This core is a full implementation of the Triple DES encryption algorithm.
AMBA 5 AHB Bus TFT LCD / OLED Display Controller
The Digital Blocks DB9000AHB5 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 5 AHB b…