Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
AMBA AXI5 / ACE5-Lite TFT LCD / OLED Display Controller
The Display Controller IP Core interfaces a microprocessor and frame buffer memory via an AMBA AXI5 / ACE5-Lite Protocol Interconnect to a TFT LCD or OLED display panel.
Multi-world Hardware Isolation for System Security
SiFive Insight is a trace and debug portfolio that accelerates HW/ SW validation for standalone SiFive RISC-V designs or mixed ve…
Virtual Machine Security with WorldGuard™ Integration
The SiFive IOMMU Gen 2 is a scalable address translation engine connecting DMA capable I/O devices to system memory.
Open And Secure Distributed Security Architecture
SiFive Shield is a comprehensive portfolio of hardware security technologies designed for RISC-V processors and SoCs.
Multi-world Hardware Isolation System IP for System Security
Delivers advanced execution environment capabilities and hardware-enforced isolation to RISC-V systems
The 112G SerDes IP is a high-performance, multi-standard serializer/deserializer solution optimized for various reach profiles and advanced packaging architectures.
Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
Expands effective bandwidth across links and memory interfaces with deterministic, data-independent latency, fully pipelined to sustain line rate
Memory Simulation & Verification Platform
MemVerify gives you a complete, working memory verification environment out of the box.
Composed of three dedicated HW IP cores (PolyCore, KeccakCore, MaskCore) and the software stack
co-processor supporting NIST’s selected Post-Quantum Cryptography (PQC) standards
Supports the polynomial arithmetic required by lattice-based cryptography algorithms
The Keccak IP core supports Keccak-based hash functions, including the SHA3 and SHAKE families.
High performance-efficient edge deep learning accelerator for small LLM/VLM/VLA and CNN/RNN/LSTM
Peripheral Sensor Interface (PSI5) Host Controller
Configurable automotive Peripheral Sensor Interface (PSI5) host controller that implements the ECU side of PSI5 communication systems
MIPI C‑PHY/D‑PHY IP on TSMC N2P
The MXL_CSI2_RX_USL_CDPHY_ECM_T_2N2P is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the …
Clustered IP to Scale Throughput
When one engine isn’t enough, Atrevido Cluster multiplies throughput under the same ISA and memory‑first design (CPU/Vector, optionally Tensor‑equipped instances)
Scaled for heavier inference and higher throughput
C1 is a compact, fully programmable RISC‑V AI IP core for real‑time inference
Embedded HSM (Root of Trust) with Arm Cortex-M33 Processor
Automotive Grade ISO 26262 ASIL-B
Planar Marchand 1:2 Balun, 57 – 67 GHz