JPEG Encoder Full HD(YUV422) 30fps@126MHz(1Sample/clk)
The KJN-F1ENC conform to the JPEG baseline format for compressing still images.
- Video Processing
- We also accept customization according to customer needs.
- ISO/IEC 10918-1, ITU-T T.81
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
JPEG Encoder Full HD(YUV422) 30fps@126MHz(1Sample/clk)
The KJN-F1ENC conform to the JPEG baseline format for compressing still images.
JPEG Codec Full HD(YUV422) 30fps@126MHz(1Sample/clk)
The KJN-F1 conform to the JPEG baseline format for compressing/decompressing still images.
MIPI CSI-2 Transmitter for FPGA
MIPI CSI-2 Tx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processer
MIPI CSI-2 Rx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processor.
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces.
V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX
Based on internal equipment connections, the V-by-One® HS technology aims to transmit video signals at high data rates.
V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections.
V-by-One Rx IP, Silicon Proven in SMIC 40LL
The V-by-One HS technology aims to transmit video signals at a high data rate using internal equipment connections.
V-by-One Tx IP, Silicon Proven in SMIC 40LL
V-by-One HS technology targets a high-speed data transmission of video signals based on the internal connection of equipment.
LVDS/FPD Link IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS transmitter.
LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
A transmitter for LVDS with a physical layer IP.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 40SP
The Display Port 1.4 Rx IP Channel's maximum capacity is supported.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in GF 65/55LPe
The HDMI receiver PHY (Physical layer), a single-port IP core, fully conforms with HDMI 1.4's requirements.
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in GF 65/55LPe
IP core that completely conforms with HDMI 1.4 requirements for physical layer HDMI transmitters For consumer electronics like DV…
MIPI D-PHY Tx IP, Silicon Proven in SMIC 55LL
The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.
MIPI D-PHY Rx IP, Silicon Proven in SMIC 55LL
The D-PHY specification, version 1.2, is perfectly complied with by the MIPI D-PHY Analog RX IP Core.