Vendor: T2M GmbH Category: Single-Protocol PHY

LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe

A transmitter for LVDS with a physical layer IP.

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GlobalFoundries 55nm LPe In Production View all specifications

Overview

A transmitter for LVDS with a physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS drivers and can handle 1.5Gbps of data rate. Both serial and parallel data are divided into 4 channels in LVDS mode. Each channel of the parallel data has a width of 7 bits. There is a 25MHz to 150MHz input clock. The serializer is completely internal and doesn't need any extra parts. The circuit is modularly constructed and desensitized to handle changes. This makes process migration easier and produces a solid design

Key features

  • LVDS compliant Tx
  • 4 groups of 4-Data
  • 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
  • Differential polarity can be flip per lane
  • Supports from 168Mbps to 1.5Gbps data rate
  • Supports reduced swing mode
  • X7 Multiplier PLL for serial clock generation
  • Configurable analog characteristics
  • PLL loop filter
  • PLL VCO gain
  • Differential voltage Common-mode voltage
  • Pre-emphasis strength
  • Silicon Proven in GF 65/55nm LPe.

Block Diagram

LVDS/FPD Link IP in 65/55LPe block diagram

What’s Included?

  • Datasheet
  • Integration guideline
  • GDSII or Phantom
  • GDSII Layer map table
  • CDL netlist for LVS
  • LEF Verilog behavior model
  • Liberty timing model DRC/LVS/ERC results

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 55nm LPe In Production

Specifications

Identity

Part Number
LVDS/FPD Link IP in 65/55LPe
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany
Contact T2M GmbH

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Frequently asked questions about Single-Protocol PHY IP

What is LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe?

LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for globalfoundries In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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