VeriSilicon SMIC 0.18¦Ìm 1.8V/3.3V VPPIO_DUP_01 IO Library
VeriSilicon SMIC 0.18um 1.8V/3.3V VPPIO_DUP_01 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing I…
SMIC 0.18um Stereo Speaker Drivers
The SMIC18_SPKDRIVER_01 specifies the design of stereo speaker drivers.
SMIC 0.18¦Ìm 5v-3.3v/1.8v Power Regulator
Based on SMIC 0.18¦Ìm 3.3v/1.8v Logic process, this design of Power Regulator is to provide both 3.3v and 1.8v power supplies whi…
This IP is a programmable Analog PLL suitable for high speed clock generation.
VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_01 I/O Cell Library
VeriSilicon SMIC 0.13μm SSTL2/SSTL3 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing …
SMIC 0.18um 12-Bit 8 Input 1M/200k SAR ADC
The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
SMIC 0.13um 3.3V Power On Reset
Present Power on Reset generates system reset pulses (POR33) when the 3.3V power supplier (VIN33) is turned on.
The present IP is a Power On Reset (POR) circuit without any external resistor or capacitor.
SMIC 0.13um 3.3v/1.2v Power Regulator
Present IP devises a NO-CAP regulator which generates 1.2V voltage from 3.3V power supply and provides100mA plus loading current.
This IP is a programmable Analog PLL suitable for generating system clock.
SMIC 0.13um 1.2v/3.3v PLL Specification
This PLL is designed for audio clock generation.
This PLL is designed for audio clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 0.13um Crystal Oscillator IO
This IP is a crystal oscillator DUP IO pad designed for low-power consumption applications.
The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream.
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
SMIC 0.18um 1.8V/3.3V Clockgating Cell Library
VeriSilicon SMIC 0.18um 1.8V/3.3V Clockgating Cell (01) Library developed by VeriSilicon is optimized for Semiconductor Manufactu…
SMIC 0.25um 2.5V/3.3V PCI I/O Cells Library
VeriSilicon SMIC 0.25um 2.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Inte…
SMIC 0.18um Low Leakage Process
SMIC18LL_VDD33SW_01, a 3.3V switchable power control block also called 3.3V power bypass control block, is developed by VeriSilic…
SSTL_18 (Stub Series Terminated Logic for 1.8v) is an electrical interface commonly used with DDR2.