LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …
Low Power All Digital Fractional-N PLL in Samsung 14LPP
Perceptia’s DeepSub™ pPLL05 is a low power, low voltage all digital PLL featuring low-jitter and compact area.
Temperature Sensor on Samsung 4nm, LN04LPP
The temperature sensor indicates the junction temperature as a 9-bit binary digital code.
Temperature Sensor on Samsung 14nm, LN14LPP
The temperature sensor indicates the junction temperature as a 12-bit binary digital code.
PVT Sensor on Samsung 4nm, LN04LPP
The PVT sensor indicates the junction temperature as a 12-bit binary digital code.
Oscillator on Samsung 28nm LNM28FDS
OSC2802X is a 1V oscillator with output frequency of 240kHz.
Integer PLL on Samsung 8nm LN08LPP
PLLF0816X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Integer PLL on Samsung 28nm LN28FDS
PLL2851X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Frac-N PLL on Samsung 8nm LN08LPP
PLLF0842X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Frac-N PLL on Samsung 4nm LN04LPP
PLLF0434X is a 1.2V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Frac-N PLL on Samsung 28nm LN28FDS
PLL2860X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
Adaptive Body Bias Generator on Samsung 28nm LN28FDS
The adaptive body bias generator (ABBG) consists of a positive-BBG and a negative-BBG for FDSOI-MOS transistors.
12-bit ADC on Samsung 8nm LN08LPP
The sf_adc0802x_ln08lpp_306011 is a 1.8V/0.75V dual supply-voltage 16-ch 12-bit analog-to-digital converter (ADC) that supports c…
12-bit ADC on Samsung 4nm LN04LPE
ADC0401X is a 1.2-V/0.75-V dual supply voltage 16-channel 12-bit Analog-to-Digital Converter (ADC) that supports conversion rate …
MIPI D-PHY v1.2 TX 4 Lanes in Samsung (8nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
MIPI D-PHY v1.2 RX 2 Lanes in Samsung (8nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…
12G Ethernet PHY in Samsung (14nm)
The silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE…
32G PHY in Samsung (10nm, 8nm, 4nm, 5nm, SF2)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
PCIe 4.0 PHY in Samsung (14nm, 11nm, SF5A, SF2)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’…
HDMI 2.1 Tx PHY in Samsung (14nm)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 speci…