Foundation Library IP cores provide the fundamental building blocks required for ASIC and SoC implementation, enabling efficient digital design, physical synthesis, timing closure, and manufacturing across advanced semiconductor process nodes.
This category includes both Standard Cell Libraries and I/O Pad Libraries, covering logic cells, sequential elements, low-power cells, level shifters, ESD-protected I/O interfaces, and process-specific implementation libraries optimized for leading foundries.
This catalog enables semiconductor engineers to evaluate and compare Foundation Library IP solutions from multiple vendors based on process node support, PPA (Power, Performance, Area) characteristics, library characterization quality, voltage domains, reliability requirements, and integration with modern EDA design flows.
Whether targeting AI accelerators, automotive SoCs, networking devices, wireless chipsets, or high-performance computing applications, engineers can identify the Foundation Library IP best suited to their technology, performance, and manufacturing requirements.
On-chip ESD/EOS/Latch up/EMC protection for high voltage and BCD processes
Design cost reduction Designing ESD protection can be very costly: frequently many test structures are required, analysis needs t…
Robust circuit and interface solutions
PhyStar® robust circuit and interface solutions, including custom digital I/O’s, circuits that handle transient disturbances (e.g.
Differential Clock Receiver to CMOS on TSMC CLN2P
The Differential Clock Receiver macro addresses a large portfolio of applications.
Differential Buffer, TSMC N5, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express 3.1 includes the vendor’s high-speed, high-performance transceiver to meet today’s appli…
VeriSyno offers a variety of digital IPs tailored to meet the demands of consumer, industrial, and automotive SoCs, enabling effi…
5V ESD Clamp in GlobalFoundries 180nm LPe
A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
All self-developed domestic IPs
VeriSyno offers network IP solutions tailored for the high-end server market.
TSMC N3P 1.2V IO Platform supporting cells
TSMC N3P 1.2V IO Platform supporting cells
On-chip ESD/EOS/Latch up protection for advanced and low voltage processes
Scalable on-chip HBM (MM) levels Some applications need higher ESD robustness levels.
TSMC N3P 1.8V IO Platform supporting cells
TSMC N3P 1.8V IO Platform supporting cells
TSMC 65LP 2Gb/s TX LVDS IO cell
The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC …
TSMC 40LP 2Gb/s TX LVDS IO cell
The LST25R/Z cell is a high-speed and low-power LVDS transmitter IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC …
TSMC 40LP 2Gb/s RX LVDS IO cell
The LSR25R/Z cell is a high-speed and low-power LVDS receiver IO cell powered at 2.5V/1.1V or 1.8V/1.1V, designed on the TSMC 40 …
OPM-G2-1.9-5.5-1.8.03_GF_22_FDX is an Over-voltage Protection Module in GF 22FDX that handles direct connection of voltage regula…
OPM-G2-1.9-5.5-1.8.02_GF_22_FDX is an Over-voltage Protection Module for regualtors in GF 22FDX that handles direct connection of…
A 65nm/55nm Wirebond IO Library with 1.2V to 3.3V GPIO and 5V ODIO
Full Custom IO Library.
The agileDSCL is a compact Digital Standard Cell Library customizable for specific foundries and processes, and optimized for low…
High-voltage solutions in baseline GlobalFoundries and multi-foundry technologies
Certus is pleased to offer High-voltage ESD solutions across multiple baseline technologies.
TSMC 65LP Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) p…
TSMC 65LP 2Gb/s bidirectional LVDS IO cell
The LSB25R/Z cell is a high-speed and low-power LVDS bidirectional transceiver IO cell powered at 2.5V/1.2V or 1.8V/1.2V, designe…