What is TSMC 65LP Combo IO with 2Gb/s LVDS and CMOS GPIO?
TSMC 65LP Combo IO with 2Gb/s LVDS and CMOS GPIO is a GPIO IP core from nSilition listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Vendor:
nSilition
Category:
GPIO
TSMC 65LP Combo IO with 2Gb/s LVDS and CMOS GPIO
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) p…
Overview
A Combo cell is an IO cell combining an LVDS receiver, driver or transceiver with a double CMOS GPIO (in, out or bidirectional) powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC 65 LP technology.
Key features
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
- Built-in, low parasitic ESD protection
- Easily integrates with TSMC I/O library cells
- All-in-ring® topology, so no core silicon area is used by LVDS
- The same cells operate with 2.5V/1.2V or 1.8V/1.2V power supplies
- Adjustable output common mode voltage (LVDS or SubLVDS mode)
- Adjustable driving current for buses with single or double termination
- Adjustable output driving current for CMOS GPIOs
- Standby/power down mode
- Internal bias voltage generation and bias current distribution circuitry
- Selectable on-chip termination resistor, with optional user tuning
- Digital loopback functions to ease ATE testing
- Up to 2 Gbps data rate LVDS
Applications
- Multi-purpose reconfigurable IO
- Point-to-point, point-to-multipoint or bus-based IC high-speed data communications
- Intra-package (e.g. MCM or SIP) inter-die high-speed data communications
- Backplane high-speed data communications
- High-speed serial communications (HDMI, SATA, PCIeX, etc.)
- Communication to LCD/OLED screens
- Video sensor digital data interface
What’s Included?
- GDS II layouts
- LEF abstracts
- CDL netlists
- Liberty timings
- Verilog description
- A full datasheet
- An integration note
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 65nm | LP | Silicon Proven |
Specifications
Identity
Part Number
nSIO2000_TS65LP 2V5_1V2_COMBO
Vendor
nSilition
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Belgium
Frequently asked questions about GPIO Pad Library IP cores
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.