Compute Acceleration IP Cores

Suppressing the degradation of image quality by the original comp./decomp.

• Data Compression

Suppressing the degradation of image quality by the original comp./decomp.

• Data Compression

In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.

• Channel Coding
• In Production
• Immediate

On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.

• Channel Coding
• In Production
• Immediate
• Home Plug

The Digital video broadcasting for cable systems systems, a FEC sub-system is needed.

• Channel Coding
• In Production
• Immediate
• yes

In Digital video broadcasting for digital transmission for satellite applications, a FEC (Forward Error Correction) sub-system is…

• Channel Coding
• In Production
• Immediate
• yes

In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.

• Channel Coding
• In Production
• Immediate
• yes

In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.

• Channel Coding
• In Production
• Immediate
• yes

The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA.

• CPU

The eSi-HP-FP-Fused-Multiply-Add IP core implements half-precision (16-bit), IEEE 754 compliant, floating-point fused multiply an…

• FPU
• Silicon proven in multiple products
• Immediate
• IEE 754

The eSi-SP-FP-Float-to-Int IP core implements single-precision (32-bit), IEEE 754 floating-point to integer conversion.

• FPU
• Silicon proven in multiple products
• Immediate
• IEEE 754

The eSi-SP-FP-Square-Root IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point square root operations.

• FPU
• Silicon proven in multiple products
• Immediate
• IEEE 754

The eSi-SP-FP-Divider IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point division.

• FPU
• Silicon proven in multiple products
• Immediate
• IEEE-754

The eSi-SP-FP-Multiplier IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point multiplication.

• FPU
• Silicon proven in multiple products
• Immediate
• IEEE-754

The eSi-SP-FP-Adder IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point addition and subtraction ope…

• FPU
• Silicon proven in multiple products
• Immediate
• IEEE-754

The Prodigy is the first Universal Processor combining General Purpose Processors, High Performance Computng (HPC), Artficial Int…

• NPU

Designed for high-end performance at best efficiency, Cortex-A78 enables superior immersive experiences, bridging the gap between…

• CPU

The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data.

• Filters Transforms
• Mature
• Now

The IPrium-J83B-C-Modulator IP Core is 32-channel J.83B Modualtor with MAX5861 (MAX5862) support.

• Modulation Demodulation
• Silicon proven
• Now
• ITU-T J.83 Annex B (12/2007)

64-bit RISC-V core with in-order dual issue pipeline based complex.

• RISC-V