Vendor: eSi-RISC Category: FPU

Single precision, IEEE 754, floating point adder

The eSi-SP-FP-Adder IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point addition and subtraction ope…

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Overview

The eSi-SP-FP-Adder IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point addition and subtraction operations.

The number of pipeline stages is configurable to balance maximum frequency, area, power and latency.

Key features

  • Single-precision (32-bit) floating point addition and subtraction.
  • IEEE 754 compliant.
  • Full support for infinities, NaNs and denormals.
  • Rounding is to the nearest even number.
  • Status flags indicating invalid, overflow, underflow and inexact.
  • Optional pipeline registers.
  • Supports one operation per cycle.

What’s Included?

  • Verilog RTL
  • Testbench
  • Simulation and synthesis scripts
  • Documentation

Specifications

Identity

Part Number
eSi-SP-FP-Adder
Vendor
eSi-RISC
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

eSi-RISC
HQ: UK
Contact eSi-RISC

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Frequently asked questions about FPU IP cores

What is Single precision, IEEE 754, floating point adder?

Single precision, IEEE 754, floating point adder is a FPU IP core from eSi-RISC listed on Semi IP Hub.

How should engineers evaluate this FPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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