Xilinx, Inc.
•
HQ:
USA
The Xilinx LogiCORE™ CORDIC IP implements a generalized coordinate rotational digital computer (CORDIC) algorithm, initially deve…
- Arithmetic Units
Compare 668 DSP Math IP Cores from 101 vendors
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Xilinx, Inc.• HQ: USA
The Xilinx® LogiCORE™ IP Convolutional Encoder core can be used in a wide variety of error correcting applications and is typical…
- Channel Coding
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Xilinx, Inc.• HQ: USA
The Xilinx LogiCORE™ Complex Multiplier IP core implements AXI4-Stream compliant, high-performance, optimized complex multipliers…
- Arithmetic Units
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Xilinx, Inc.• HQ: USA
The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations.
- Arithmetic Units
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Aliathon Ltd• HQ: United Kingdom
Aliathon’s 2.5Gbps GFP-T Encoder Core provides a flexible, resource-efficient, high-density programmable logic based solution for…
- Channel Coding
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Silicon Infusion Ltd.• HQ: UK
The Zaltys High Data Rate Demodulator (HDRM-D) and the Zaltys Enhanced High Data Rate Demodulator (HDRM-D2) IP cores efficiently …
- Modulation Demodulation
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Aldec, Inc.• HQ: USA
Viterbi encoding is widely used for satellite and other noisy communications channels.
- Channel Coding
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Aldec, Inc.• HQ: USA
IP-ALIDCT soft core is the unit to perform the Inverse Discrete Cosine Transform (IDCT).
- Filters Transforms
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Aldec, Inc.• HQ: USA
IP-ALDCT soft core is the unit to perform the Discrete Cosine Transform (DCT).
- Filters Transforms
- Now
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Xilinx, Inc.• HQ: USA
The Accumulator IP provides LUT and single DSP48 slice accumulation implementations.
- Arithmetic Units
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Very High Speed 16 State MAP Decoder
Small World Communications• HQ: AustraliaThis is a very high speed 16 state maximum a posteriori (MAP) soft-in-soft-out (SISO) triple interleaved error control decoder wi…
- Channel Coding
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Small World Communications• HQ: Australia
This is a high speed 16 state maximum a posteriori (MAP) soft-in-soft-out (SISO) error control decoder with log-likelihood-ratio …
- Channel Coding
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Arasan Chip Systems Inc.• HQ: USA
The NAND Flash landscape is changing and the Arasan NAND flash management technology is changing with it.
- Channel Coding
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Multiplexer 2x 16 to 1 - XFAB 180nm
CoreHW• HQ: FinlandMultiplexer 2x 16 to 1 - XFAB 180nm
- Control Logic
- Silicon Verified
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Binary to One-hot coder, 6bit - XFAB 180nm
CoreHW• HQ: FinlandBinary to One-hot coder, 6bit - XFAB 180nm
- Control Logic
- Silicon Verified
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Binary to One-hot coder, 4bit - XFAB 180nm
CoreHW• HQ: FinlandBinary to One-hot coder, 4bit - XFAB 180nm
- Control Logic
- Silicon Verified
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RF Counter, 16b - STMicroelectronics 65nm
CoreHW• HQ: FinlandRF Counter, 16b - STMicroelectronics 65nm
- Control Logic
- Pre-Silicon
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Xilinx, Inc.• HQ: USA
Included with Xilinx ISE Software The BUFT-based Multiplexer Slice IP core supports buses of up to 64 bits wide and 1 to 64 input…
- Control Logic
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Xilinx, Inc.• HQ: USA
The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width.
- Control Logic
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Xilinx, Inc.• HQ: USA
Included with Xilinx ISE Software The BUFE-based Multiplexer Slice IP core supports buses of up to 64 bits wide and 1 to 64 input…
- Control Logic