Verification Platform for Complex Designs
By Amit Adua, Cadence Design Systems
December 31, 2007 -- edadesignline.com
Introduction
As the complexity of electronic designs continues to increase, the challenge of verifying their functional correctness is increasing as well. The problem is compounded with the increasing market demands to deliver the next more complex version of product in even lesser time and with tighter cost constraints. Under these circumstances, ensuring the functional correctness of the modern devices in given time can not be satisfactorily achieved by simply scaling up the verification resources using the traditional techniques. This makes it absolutely necessary for the companies that provide verification solutions ("the EDA verification companies") to deliver new products & techniques to do the verification tasks.
In this article the challenges faced in verifying today's complex designs are discussed. Along with, the corresponding advancements required in verification products and techniques to overcome these issues have been suggested. In a way, this article provides an insight of today's verification problems faced by semiconductor companies and also suggests what should be considered in the verification platforms to overcome these challenges.
December 31, 2007 -- edadesignline.com
Introduction
As the complexity of electronic designs continues to increase, the challenge of verifying their functional correctness is increasing as well. The problem is compounded with the increasing market demands to deliver the next more complex version of product in even lesser time and with tighter cost constraints. Under these circumstances, ensuring the functional correctness of the modern devices in given time can not be satisfactorily achieved by simply scaling up the verification resources using the traditional techniques. This makes it absolutely necessary for the companies that provide verification solutions ("the EDA verification companies") to deliver new products & techniques to do the verification tasks.
In this article the challenges faced in verifying today's complex designs are discussed. Along with, the corresponding advancements required in verification products and techniques to overcome these issues have been suggested. In a way, this article provides an insight of today's verification problems faced by semiconductor companies and also suggests what should be considered in the verification platforms to overcome these challenges.
To read the full article, click here
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related Articles
- Unique Approach to Verification of Complex SoC Designs
- FPGA based Complex System Designs: Methodology and Techniques
- Dealing with memory access ordering in complex embedded designs
- Platform Software Verification Approaches For Safety Critical Systems
Latest Articles
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
- Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing