Using SystemVerilog for functional verification
Tom Fitzpatrick, Mentor Graphics Design Verification & Test Division
(12/05/2005 9:00 AM EST)
EE Times
The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or functional errors are the leading cause of ASIC respins (Figure 1).
With 75 percent of respins caused by these errors, the need for a higher quality approach to verification has been clearly identified. Design and verification engineers face the question of how to move from their existing functional verification processes toward a more advanced functional verification methodology that includes automated testbench techniques such as assertions, constrained-random data generation, and functional coverage.
(12/05/2005 9:00 AM EST)
EE Times
The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or functional errors are the leading cause of ASIC respins (Figure 1).
With 75 percent of respins caused by these errors, the need for a higher quality approach to verification has been clearly identified. Design and verification engineers face the question of how to move from their existing functional verification processes toward a more advanced functional verification methodology that includes automated testbench techniques such as assertions, constrained-random data generation, and functional coverage.
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