Using an open debug interconnect model to simplify embedded systems design
An open debug interconnect model is proposed for understanding debugger component interactions.
By Tom Cunningham, Freescale Semiconductor
(08/29/07, 12:05:00 AM EDT) -- Embedded.com
Technology people are generally familiar with the Open Systems Interconnection model for computer networks and protocols, often referred to as the OSI Reference Model (ISO 7498)[1]. The Basic Reference portion of the model consists of seven layers which build upon each other with increasing levels of abstraction (See Figure 1 below).
This article postulates that a similar abstraction may be applied to the embedded debugging world, with functional layers analogous to the OSI model. Further, individual layers can be assigned to particular debug entities, just like, for example, the association of the OSI network layer to routers, or the application layer association with a host.
Figure 1. OSI Layers and Example implementations
By Tom Cunningham, Freescale Semiconductor
(08/29/07, 12:05:00 AM EDT) -- Embedded.com
Technology people are generally familiar with the Open Systems Interconnection model for computer networks and protocols, often referred to as the OSI Reference Model (ISO 7498)[1]. The Basic Reference portion of the model consists of seven layers which build upon each other with increasing levels of abstraction (See Figure 1 below).
This article postulates that a similar abstraction may be applied to the embedded debugging world, with functional layers analogous to the OSI model. Further, individual layers can be assigned to particular debug entities, just like, for example, the association of the OSI network layer to routers, or the application layer association with a host.
Figure 1. OSI Layers and Example implementations
The intent here is to explore levels of debugging functionality, with the OSI model as a guide, and identify hierarchical layers and associations among hardware and software to produce a model of debugging interrelationships. It is hoped that such a model may provide clarity in understanding the myriad ways debugger components interact.
To read the full article, click here
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- How to manage changing IP in an evolving SoC design
- Using edge AI processors to boost embedded AI performance
- An Industrial Overview of Open Standards for Embedded Vision and Inferencing
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection