Top 5 predictions for eFPGA in 2022
By Andy Jaros, Flex Logix
embedded.com (January 30, 2022)
With the eFPGA now readily available in many process nodes from multiple suppliers, Flex Logix offers predictions on what we can expect to see around eFPGA development and use cases in 2022 and beyond.
The need for reconfigurability in systems on chip (SoCs) will continue to increase in 2022 along with the rapidly rising cost of developing SoCs especially at advanced process nodes. As prices increase, so does the pressure for SoC providers to generate a lot of revenue on their products. This can be possible if reconfigurability allows the SoC to be used in a wider range of applications. The embedded FPGA (eFPGA) approach can deliver that flexibility.
In the past, eFPGA was typically not the first intellectual property (IP) a chip architect would consider for a project. After all, there have been hundreds of thousands, if not millions, of chips designed without it. However, that mindset has been steadily changing and the most significant reason now is because customer requirements are more demanding.
They need more performance and lower power and at the same time, the cost and design cycles for chip development continues to skyrocket. These constantly changing demands require a changeable solution.
To read the full article, click here
Related Semiconductor IP
- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
- Radiation-Hardened eFPGA
- eFPGA Hard IP Generator
- eFPGA Soft IP
- eFPGA on GlobalFoundries GF12LPP
Related Articles
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Top 5 Reasons why CPU is the Best Processor for AI Inference
- Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
- Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices