Tiles - An Architectural Abstraction for Platform-Based Design
by Drew Wingard
The relentless pace of Moore's Law has caught up with us again. Design teams still struggling under the weight of system-on-a-chip (SOC) designs composed of hopefully-reusable-next-time IP cores are running head-first into a new challenge-trying to manage the interactions of 50 or more somewhat independent cores throughout the design process. What is needed is a new level of abstraction-a level of hierarchy that reduces the number of objects to something a designer can effectively reason over. Some people call this next level of abstraction the platform, but most platform definitions imply a single "metacore" integrating a critical subset of the desired functions that is then integrated with a set of application-specific peripherals.
The relentless pace of Moore's Law has caught up with us again. Design teams still struggling under the weight of system-on-a-chip (SOC) designs composed of hopefully-reusable-next-time IP cores are running head-first into a new challenge-trying to manage the interactions of 50 or more somewhat independent cores throughout the design process. What is needed is a new level of abstraction-a level of hierarchy that reduces the number of objects to something a designer can effectively reason over. Some people call this next level of abstraction the platform, but most platform definitions imply a single "metacore" integrating a critical subset of the desired functions that is then integrated with a set of application-specific peripherals.
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- The role of sockets in platform based design: a case study of the OMAP platform
- System CoreWare Based Design using RapidChip Platform ASIC
- The Platform Based SOC Design that Utilizes Structured ASIC Technology
- The value of selecting IP based on a platform
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs