Using switched capacitors to create programmable analog logic blocks in mixed-signal designs
Sachin Gupta, Cypress Semiconductor
EETimes (8/18/2010 2:18 AM EDT)
Any physical system design needs both analog and digital functionality. Achieving a modular, programmable design is crucial for the demanding applications of future, which has led to more and more designs integrating subsystems and using mixed-signal architectures.
Scalability as well as dynamic changes in customer requirements are two of the challenges designers face when implementing a system using fixed-function components. A modular, programmable design helps overcome the issues associated with the porting of designs to different devices at a later stage in a product’s lifecycle.
For these kinds of applications, a programmable design allows a more flexible approach compared to fixed-function implementations. Achieving such flexibility in the analog domain, however, has been a challenge for developers. The use of switched capacitor circuits greatly helps resolve this issue
Switched capacitor blocks are the basic building blocks of a programmable analog solution. They enable the integration of both analog and digital functions onto a single chip and define today’s true system-on-chip (SoC) architectures. Conventional analog signal processing circuits use continuous time circuits consisting of resistors, capacitors and operational amplifiers.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Articles
- Embedded Systems: Programmable Logic -> Programming enters designer's core
- Embedded Systems: Programmable Logic -> Common gateway networks enable remote programs
- Embedded Systems: Programmable Logic -> FPGAs don remote reprogram habits
- Embedded Systems: Programmable Logic -> Embarrassment of riches hinders proper use of Moore's Law
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST