Stretching the Dynamic Range of ADCs - A case study
Robert Fifield, RFEL
EETimes (10/9/2012 10:26 AM EDT)
Whether your application is focused on wireless communications or instrumentation, the performance bottleneck is often the dynamic range of the analog-to-digital converter (ADC). Dynamic range is often a key parameter within signal processing systems and a shortfall can limit the quality and range of signals that can be received. The technical progress made on improving this gateway between the analog and digital world has not kept pace with Moore’s law[1] because the challenges are more fundamental than simply reducing transistor sizes. Methods to increase ADC dynamic range are always of interest although each solution often suits particular applications.
As an example of pushing ADC dynamic range beyond what is currently available, the engineers at RFEL were confronted with an application where a customer required an analog-to-digital conversion with a 74dB dynamic range at 800MSPS. Most available ADCs at this rate were typically 52dB, i.e. 8.3 effective number of bits[2] (ENOB). This represented a significant 22dB shortfall, which had to be resolved for the project to be feasible.
Various techniques for extending dynamic range were considered taking into account their advantages and disadvantages:
To read the full article, click here
Related Semiconductor IP
- PVT sensor integrated SAR ADC in 12nm
- 12bit 500Msps High Speed General Purpose SAR ADC IP Core
- 12bit 4Gsps SAR General Purpose ADC IP Core
- 16bit 5Msps SAR General Purpose ADC IP Core
- 24-bit 320kHz Bandwidth ADC IP
Related Articles
- Inside HDR10: A technical exploration of High Dynamic Range
- Variable-integration-time image sensor for wide dynamic range
- New Applications Areas Driving Higher Dynamic Range Converters
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices