Dealing with SoC metastability problems due to Reset Domain Crossing
Arjun Pal Chowdhury , Neha Agarwal and Ankush Sethi, Freescale Semiconductor India Pvt LTD
embedded.com (November 10, 2013)
Metastability in design due to asynchronous clock domain crossing (CDC) is a well known problem. Industry standard advanced tools are available to catch such structural or functional issues in design.
However, CDC is not the only reason a signal becomes asynchronous with respect to the destination clock domain. In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will create an asynchronous crossing path and cause metastability at destination register. Referred to as Reset Domain Crossing (RDC), it occurs when the reset signals of launch and capture flops are different.
This article will review some of the conditions under which RDC occurs and propose some ways to deal with the problems that occur up front in the design phase.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Articles
- SoC tool flow techniques for detecting reset domain crossing problems
- Understanding Clock Domain Crossing Issues
- Clock Domain Crossing Glitch Detection Using Formal Verification
- The Challenge of the Clock Domain Crossing verification in DO-254
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST