Silicon platform optimization: A top-down methodology
Rohit Mittal & Anand Konanur
EDN (November 12, 2014)
Recently there has been an explosion of short-range wireless applications. Some well-known examples include NFC payment systems and wireless charging etc. These applications require an interaction of electromagnetic, electrical, and mechanical domains. Unfortunately there is no tool that can solve the complete system efficiently for rapid silicon and system specification. The net effect is that either the silicon is not properly specified or the system needs to be redesigned.
Traditional electrical simulators such as SPICE are effective in solving lumped element equations. However, such tools cannot model EM fields present in sensors, especially when they are embedded in the vicinity of other components and metallic chassis. Other products can solve Maxwell's equations using the FEM (Finite Element Method) but are woefully inefficient in importing transistor parameters. We will present a unified methodology that takes into account the best of both tools to create a tops-down view of the complete system. A representative system is shown but this methodology can be extended to other interdisciplinary optimization problems.
To read the full article, click here
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- Top-down SoC Design Methodology
- Design for verification methodology allows silicon success
- Implementing Power Management IP for Dynamic and Static Power Reduction in Configurable Microprocessors using the Galaxy Design Platform at 130nm
- Follow the right steps for evaluating platform methodology
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection