Reusability, usability and flexibility
Raja Bavani, Mindtree
EETimes (8/18/2010 3:31 AM EDT)
Discussions on reusability and reusable components are widespread among the practitioners of software engineering as well as the academia. A library of reusable components, one among the strategic engineering assets of any successful IT organisation contributes not only to productivity improvements but also to product quality throughout the life cycle of any software product.
Usability is one of the utmost qualities of any reusable component and any reusable component will succeed in serving its purpose only if the application or product that consumes it, is designed flexible enough to reap the advantages of reuse.
Think of a reusable component that can serve as a probe to measure the performance of any business application at run time on need basis. Its value becomes multifold when it can be used across multiple applications to derive performance parameters. While our expectation and imagination are endless, there are practical constraints that may not enable every software engineer to innovate reusability to such a larger extent.
To read the full article, click here
Related Semiconductor IP
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
Related Articles
- High-Performance DSPs -> Reconfigurable coprocessors create flexibility in DSP apps
- MPEG Standards -> Object-based MPEG offers flexibility
- MEMS -> D-MEMS yield new flexibility for optical nets
- SoC Configurable Platforms -> Taking flexibility to the max in platforms
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing