Reducing energy cost of intra-chip communications
Fabien Clermidy, Ivan Miro-Panades, Yvain Thonnart and Pascal Vivet, CEA-Leti
EETimes (5/15/2012 8:08 AM EDT)
With the advent of new highly computing-intensive mobile applications (high throughput and software-defined radio, high-resolution video streaming, 3D image processing, augmented reality…), current system-on-chips (SoCs) are quickly moving towards many-cores for increasing parallelism. As a result, the number and distance of communications between these cores are growing exponentially. This point is explaining the relative importance of communications which can account for up to 30 percent of overall energy consumption in the highest performing many-core architectures.
From multi-cores to many-cores
For achieving high-performance systems, it is well-known that the race towards higher frequency has moved towards a race in terms of number of cores. This is true for desktop, but also for laptop, tablets and mobile phones with an even quicker evolution speed. Figure 1 shows a typical evolution of current SoCs: A multi-core host processor is used for sustaining the required performance for web applications while a sea of Processing Engines (PE) is used for sustaining highly parallel and computing-intensive applications. Then, each application will use parts of these PE in a configurable manner, while the corresponding software stack will run on the host processors.
To read the full article, click here
Related Semiconductor IP
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
Related Articles
- Do the Math: Reduce Cost and Get the Right Communications System I/O Connectivity
- Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction
- Parsing the Mindboggling Cost of Ownership of Generative AI
- Data Movement Is the Energy Bottleneck of Today’s SoCs
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing