Use Pre-Configured Device Drivers (PCD) to reduce embedded system memory footprint
By Ashutosh Sharma, STMicroelectronics
Embedded.com (10/22/08, 12:15:00 AM EDT)
In embedded systems, the predominant bottle-neck is the size of the binaries and the RAM used. The large memory size results in an increase in the cost of the final system due to the large FLASH and RAM.
However, by using preconfigured device (PCD) driver techniques developers can significantly reduce the usage of memory to minimize the cost of the final product with only slight changes in the conventional development method/technique.
PCD does not require any extra hardware or critical software development. At present, the developed code is rewritten, such that the final binary is smaller in size. Moreover, the start-up of the device driver is faster compared to the original one.
Embedded.com (10/22/08, 12:15:00 AM EDT)
In embedded systems, the predominant bottle-neck is the size of the binaries and the RAM used. The large memory size results in an increase in the cost of the final system due to the large FLASH and RAM.
However, by using preconfigured device (PCD) driver techniques developers can significantly reduce the usage of memory to minimize the cost of the final product with only slight changes in the conventional development method/technique.
PCD does not require any extra hardware or critical software development. At present, the developed code is rewritten, such that the final binary is smaller in size. Moreover, the start-up of the device driver is faster compared to the original one.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- How to write DSP device drivers
- Customized DSP -> Applications take the driver's seat
- IP Integration - Size Matters! - Reducing the size of a USB 2.0 device core
- FPGAs: Embedded Apps : Designing an FPGA-based network communications device
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow