Pragmatic Adoption of Formal Analysis
Anders Nordstrom, Cadence Design Systems, Inc.
(03/29/2007 9:10 AM EDT), EE Times
Introduction
Verification of today's system-on-chip (SoC) designs is a hard problem that keeps getting harder. Design size and complexity continually increase, while the market demands ever-tighter development schedules. Multiple approaches such as directed and coverage-driven random simulations, assertion-based verification, and formal analysis are needed to most effectively verify a chip. This article focuses specifically on the technique of formal analysis and discusses how to adopt it efficiently on SoC projects.
(03/29/2007 9:10 AM EDT), EE Times
Introduction
Verification of today's system-on-chip (SoC) designs is a hard problem that keeps getting harder. Design size and complexity continually increase, while the market demands ever-tighter development schedules. Multiple approaches such as directed and coverage-driven random simulations, assertion-based verification, and formal analysis are needed to most effectively verify a chip. This article focuses specifically on the technique of formal analysis and discusses how to adopt it efficiently on SoC projects.
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