Power-aware FPGA design (Part 3)

Part 1

– Abstract
– Introduction
– FPGA Power Components and System Profile
– Fighting Static Power
– Fighting Dynamic Power

Part 2
– Fighting Dynamic Power (continued)

Part 3
– Fighting Dynamic Power (continued)
– Proposed Power Reduction Methodology
– Conclusions
– References

Fighting logic and nets' dynamic power

Several papers have been dedicated to this subject alone [BASZ2000, Belhadj 2002]. Due to lack of space, the focus of the following sections will be dedicated only to a power profiling of some arithmetic DesignWare elements, and a brief discussion of techniques to eliminate or reduce the propagation of unnecessary glitches.

Power-aware synthesis options/constraints setting

Because of the pressure to meet timing requirements, many FPGA designers do give much attention to the synthesis process and use stringent global timing constraints. This usually leads to larger utilization of the FPGA logic elements and the associated routing resources.

Logic resources could be reduced by studying the slack distribution for each clock domain, which is the number of paths violating the required timing specification and the overall severity of these violations. For the blocks that have relaxed timing or sufficient margin in all internal paths, careful area-oriented synthesis will lead to a sizeable reduction of the needed logic resources and thus lower power dissipation for these blocks. The caveat is the need to analyze the result of the area-oriented mapping by performing a timing analysis and being alert for glitch propagation paths due to an artificially higher number of logic levels.

To summarize, setting synthesis options and constraints should be the focus, applied appropriately to timing-critical blocks or sub-blocks. Analysis of slack distribution and avoidance of global synthesis settings are keys to improving logic dynamic power dissipation.


14. Slack distribution analysis and synthesis goals setting.
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