Platform-based design: Blocks and buses lead the way
By Gabe Moretti, Technical Editor -- 8/21/2003
EDN
Engineers deal with complex systems by dividing them into subsystems, almost always using functions as the deciding criterion. When you look at a complex ASIC, for example, you see a number of functional blocks connected by buses. Depending on the application market the ASIC is targeting, many of the blocks are common or have functions in common with other products targeting the same market, regardless of the company and design team that implemented it. A chip that targets a graphics application, for example, is likely to contain a graphics-accelerator engine, a graphics memory to buffer display data, a microcontroller, and memory for software that controls the operation of the system. Semiconductor companies and fabless foundries have developed many products with architectures that target popular application areas, such as graphics acceleration and both wired and wireless communications. Vendors market these products under the category name of ASSPs (application-specific standard products). Products in this area generally offer no way to customize the application within the chip. You must implement your functions using components outside the device.
Click here to read more ....
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Articles
- Semiconductors and software lead the way to sustainability
- How to Elevate RRAM and MRAM Design Experience to the Next Level
- The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST