New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI

By Anton Shilov, embedded.com (March 26, 2024)

The next generation of AI clusters will require more GPUs and more machines which will require either optical interconnects or PCIe active electrical cables. We dive into the details of Astera Labs new Aries 6 PCIe Gen6 retimers that support the CXL 3.x protocol.

Astera Labs recently introduced is Aries 6 PCIe Gen6 retimers that support the CXL 3.x protocol that may become an indispensable component of next-generation servers whether they are meant for artificial intelligence (AI) training, high-performance computing (HPC), storage, or general-purpose applications. The company said it has shipped samples of the chip to all hyperscale cloud service providers (CSPs) and large server makers. The chip designer expects the product to ramp starting from 2025 in AI servers and be more widely used in 2026 and onwards.

Its new Aries 6 PCIe/CXL smart DSP retimers are multifunctional bidirectional, 8-lane or 16-lane PCIe 6.2 retimers that support bifurcation, recognize the CXL 3.2 protocol, and allow for data-transfer speeds of up to 64 GT/s. The primary function of these retimers is to increase the PCIe trace distance between the root complex and its endpoints by up to three times (or to around 10 inches) while maintaining signal integrity, which is achieved by dynamically compensating for channel losses of up to 40 dB at 64 GT/s (which is better than what the PCIe specification requires, but more on this later).

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