OCP SoC instrumentation solutions involve more than just trace
Rapid analysis at the systems level helps get your applications to market quickly.
By Neal Stollon, HDL Dynamics
(11/17/07, 02:00:00 PM EST) -- Embedded.com
On-chip analysis can effectively improve our understanding of complex embedded systems, such as Open Core Protocol (OCP)-based architectures. OCP is a standards-based embedded-bus interface and multicore IP integration protocol defined by the OCP-IP industry consortium. For OCP level systems integration, real-time performance analysis is often a priority for getting products to market quickly, and embedded instrumentation analysis that can be used with emulators, prototypes, and production silicon can provide systems information and control that go beyond simulation based analysis
System On-Chip Instrumentation (System OCI) is an intellectual- property (IP) subsystem that gives designers the ability to control, trace, and debug embedded signals in a way that provides visibility into system interfaces and operations. System OCI typically works with processor-specific run-control and trace interfaces and other IP debugging systems to provide a comprehensive view of the on-chip operations. The on-chip systems analysis also enables systems designers to optimize the performance of multicycle operations for an OCP interface and the global subsystem of shared interfaces and peripherals.
In complex system architectures, designers always face tradeoffs that effect architecture initialization, stalling and deadlocking, transmission efficiency, latency, saturation, resource conflicts, and other bus operations, all of which can have a direct impact on the performance and overall system operation. Analysis at this level requires visibility and control of key signals, both to configure the OCP parameters and to determine if the result is meeting the system requirements. For embedded OCP interfaces, the instrumentation must allow adequate bus-signal visibility, without halting or impacting system operations and allow modification of parameters directly and simply.
By Neal Stollon, HDL Dynamics
(11/17/07, 02:00:00 PM EST) -- Embedded.com
On-chip analysis can effectively improve our understanding of complex embedded systems, such as Open Core Protocol (OCP)-based architectures. OCP is a standards-based embedded-bus interface and multicore IP integration protocol defined by the OCP-IP industry consortium. For OCP level systems integration, real-time performance analysis is often a priority for getting products to market quickly, and embedded instrumentation analysis that can be used with emulators, prototypes, and production silicon can provide systems information and control that go beyond simulation based analysis
System On-Chip Instrumentation (System OCI) is an intellectual- property (IP) subsystem that gives designers the ability to control, trace, and debug embedded signals in a way that provides visibility into system interfaces and operations. System OCI typically works with processor-specific run-control and trace interfaces and other IP debugging systems to provide a comprehensive view of the on-chip operations. The on-chip systems analysis also enables systems designers to optimize the performance of multicycle operations for an OCP interface and the global subsystem of shared interfaces and peripherals.
In complex system architectures, designers always face tradeoffs that effect architecture initialization, stalling and deadlocking, transmission efficiency, latency, saturation, resource conflicts, and other bus operations, all of which can have a direct impact on the performance and overall system operation. Analysis at this level requires visibility and control of key signals, both to configure the OCP parameters and to determine if the result is meeting the system requirements. For embedded OCP interfaces, the instrumentation must allow adequate bus-signal visibility, without halting or impacting system operations and allow modification of parameters directly and simply.
To read the full article, click here
Related Semiconductor IP
- Root-of-Trust IP - High-Assurance Security for Advanced and Regulated Applications
- Root-of-Trust IP - Enhanced-Assurance, Configurable Security for Scalable Semiconductor Designs
- Root-of-Trust IP - Compact, Configurable Security for Flexible Semiconductor Designs
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
Related Articles
- On-chip instrumentation aids OCP debugging
- Scalable Verification Environment Using OCP Compliant Cores and eRM Compliant eVCs
- A Methodology for Verifying OCP Interfaces
- OCP Interface for SoC - Verifying the Implementation of Embedded Processors
Latest Articles
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains