Using micro-benchmarks to evaluate & compare Networks-on-chip MPSoC designs

By Zhonghai Lu, Axel Jantsch, Erno Salminen and Cristian Grecu
Embedded.com (09/28/08, 04:25:00 PM EDT)

Network-on-Chip (NoC) has been recognized as a promising architecture to accommodate tens, hundreds or even thousand of cores. As a result, a number of NoC architectures have been and are being proposed.

On one hand, this diversity offers designers a large selection of possibilities. On the other hand, this raises an urgent need to fairly evaluate and compare different NoC architectures in order to assist designers in making right decisions and to further advance and accelerate the state-of-the-art.

Classic benchmarks for multiprocessor systems, for example, SPEC [1] and E3S [2], are application-oriented, and cannot be used directly for communication-intensive architecture such as NoCs. Moreover, the nature of the applications running on NoC-based designs is expected to be more varied and heterogeneous compared to typical applications for multiprocessor computers.

To complement application benchmarks, OCP-IP has initiated a NoC benchmark endeavor [3], one part of which are NoC micro-benchmarks. While benchmark programs evaluate the combined effect of many aspects of the platform as well as of the application, micro-benchmarks isolate individual properties and allow for a faster and deeper point analysis.

Micro-benchmarks define synthetic workloads intending to exercise a NoC in a specific way or measure a single particular aspect. Hence, a measurement offers insight in a specific property and facilitates the analysis and design of a communication infrastructure.

A single micro-benchmark provides only a very limited view and does not allow for far reaching conclusions about the suitability for an application domain. However, a set of well designed micro-benchmarks can give both a broad and detailed understanding of a given communication network.

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