Boost verification accuracy with low-power assertions
Krishna Balachandran, Synopsys
EE Times (07/28/2008 12:00 AM EDT)
Low-power designs have raised the bar on the verification effort. Designs optimized for power often employ complex design techniques that introduce their fair share of new bugs that are hard to track and fix. A single undetected power-management bug can result in functional failures manifesting in silicon.
Tight product development schedules have put immense pressure on verification teams to hunt for these bugs. The verification complexity involved with low-power designs has led to a quest to simplify and automate the bug-finding process. This is where assertions come into the picture.
Assertions themselves have been well-known to verification engineers for some time now. Assertions can be expressed in testbenches in languages such as SystemVerilog. Functional simulators monitor specified assertions and generate messages indicating whether they have passed or failed. A failed assertion is an indication of a design problem. Assertions can therefore serve as a valuable tool to help pinpoint the type and location of functional failures early in the design cycle. Assertions that find bugs at the RTL stage can potentially save months of verification time or even help avert a potential respin for bugs that go undetected until they manifest themselves in silicon.
EE Times (07/28/2008 12:00 AM EDT)
Low-power designs have raised the bar on the verification effort. Designs optimized for power often employ complex design techniques that introduce their fair share of new bugs that are hard to track and fix. A single undetected power-management bug can result in functional failures manifesting in silicon.
Tight product development schedules have put immense pressure on verification teams to hunt for these bugs. The verification complexity involved with low-power designs has led to a quest to simplify and automate the bug-finding process. This is where assertions come into the picture.
Assertions themselves have been well-known to verification engineers for some time now. Assertions can be expressed in testbenches in languages such as SystemVerilog. Functional simulators monitor specified assertions and generate messages indicating whether they have passed or failed. A failed assertion is an indication of a design problem. Assertions can therefore serve as a valuable tool to help pinpoint the type and location of functional failures early in the design cycle. Assertions that find bugs at the RTL stage can potentially save months of verification time or even help avert a potential respin for bugs that go undetected until they manifest themselves in silicon.
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