Understanding in-loop filtering in the HEVC video standard
Mihir Mody, Texas Instruments
EDN (June 21, 2013)
High Efficiency Video Coding (HEVC) is a video compression standard, a successor to H.264/MPEG-4 AVC (Advanced Video Coding), jointly developed by the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) as ISO/IEC 23008-2 MPEG-H Part 2 and ITU-T H.265. HEVC promises half bit-rate compared to current de-facto standard H.264 at a similar video quality and is expected to be deployed in a wide variety of video applications ranging from cell phones, broadcast, set-top box, video conferencing, video surveillance, automotive, etc.
The figure below shows the block diagram of the HEVC Video decoder with loop filtering, as shown with loop filtering highlighted. As shown, it is a cascading of two stages - namely de-blocking filtering (DBLK) and Sample adaptive offset (SAO) filtering to remove blocking artifacts causing during video encoding. The next two sections describe these two stages in detail.
To read the full article, click here
Related Semiconductor IP
- 4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder
- H.265 HEVC Decoder
- Video CODEC - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
- Video Decoder - AV1, HEVC, AVC, VP9
- HEVC 4Kp60 Decoder, Supports 4:2:2, 10-bit decoding and 150Mbps bitrate
Related Articles
- Emerging H.264 standard supports broadcast video encoding
- Lossless Medical Video Compression Using HEVC
- Consumer IC Advances -> Christmas list: tricks to enhance audio, video
- SPI standard to the rescue
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM