What is 4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder?
4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder is a Video Processing IP core from ParaQum Technologies listed on Semi IP Hub.
Vendor:
ParaQum Technologies
Category:
Video Processing
4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder
HEVC video decoder IP core by ParaQum Technologies is an all-hardware, high performance video decoder which is easily integrable …
Overview
HEVC video decoder IP core by ParaQum Technologies is an all-hardware, high performance video decoder which is easily integrable to complex FPGA based SoCs and supports upto 4K video decoding upto 60fos on Xilinx 7 series FPGAs. The core architecture is optimized for very low resource utilization. Coupled with low running frequencies, ParaQum HEVC Decoder IP core is ideal for deployment in mid-range FPGAs.
ParaQum HEVC decoder is world's first 4K real time HEVC decoder implemented on an FPGA with sub 150MHz clock frequencies.
High Efficiency Video coding (H.265) is the emerging video compression standard that promises 50% bit rate reduction compared to its predecessor H264. This IP core takes HEVC compliant elementary streams and outputs raw video. The decoder interfaces are AXI compliant for easy integration.
ParaQum HEVC decoder is world's first 4K real time HEVC decoder implemented on an FPGA with sub 150MHz clock frequencies.
High Efficiency Video coding (H.265) is the emerging video compression standard that promises 50% bit rate reduction compared to its predecessor H264. This IP core takes HEVC compliant elementary streams and outputs raw video. The decoder interfaces are AXI compliant for easy integration.
Key features
- Compliance standard – HEVC (H.265) Main profile Level 5.1
- Max output bitrate - 4K@60fps / 1080p@240fps
- Max input bitrate - 40Mbps
- Input Format – H.265 Elementary streams
- Output color format – YUV
- Chroma formats - 4:2:0/4:2:2/4:4:4
- Pixel Bit depth 8bits,10bits,12bits
- Max frequency - 150 MHz
- Device family support - Zynq 2000, Kintex 7, Virtex 7
- Real time decoding with maximum latency of 8ms
- Simultaneous decoding of up to 16 video channels (optional)
- Supports All-Intra Low-delay and Random-access configurations
- Optional AAC audio decoder
Block Diagram
Paraqum HEVC Decoder block diagram
Benefits
- Tailored architecture for efficient FPGA implementation
- Ability to decode 4K HEVC on mid-range FPGAs
- Low resource usage to enable SoC integration on single FPGA
Applications
- Digital cinema
- Broadcast contribution links
What’s Included?
- FPGA proven synthesizable RTL/netlist source code
- RTL test bench
- Datasheet/Integration Guide
- Verification Guide
Specifications
Identity
Part Number
Paraqum HEVC Decoder
Vendor
ParaQum Technologies
Type
Silicon IP
Videos
This video demonstrates real time decoding of 4K 30fps using Paragon HEVC decoder on Xilinx Zynq ZC 706 FPGA. Paragon HEVC decoder is capable of decoding 4K videos up to 45 fps and supports bit depths up to 12.
4:2:0 , 4:2:2 and 4:4:4 profiles are suppor
This video demonstrates real time decoding of 4K 30fps using Paragon HEVC decoder on Xilinx Zynq ZC 706 FPGA. Paragon HEVC decoder is capable of decoding 4K videos up to 45 fps and supports bit depths up to 12.
4:2:0 , 4:2:2 and 4:4:4 profiles are supported in Paragon HEVC decoder
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Sri Lanka
Frequently asked questions about Video Processing IP
How should engineers evaluate this Video Processing?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.