Implementation basics for autonomous driving vehicles
By Jan Pantzar (VSORA) and Lauro Rizzatti
The automotive industry is delivering the first implementations of advanced driver-assistance systems (ADAS) for Level 2 (foot off the gas or break) and Level 3 (hands off the wheel) vehicles. Though it’s struggling to develop an autonomous driving (AD) system from L4 (eyes off the road) to L5 (completely self-driving and autonomous) vehicles. The challenge is turning out to be more difficult than anticipated a few years ago.
Implementing an AD system comes down to safely moving a vehicle from point A to point B without human assistance. This can be accomplished by a three-stage state machine called driving control loop that includes perception, motion planning, and motion execution. Perception learns and understands the driving environment, as well as the vehicle position or its localization on a map. The perception stage feeds environment and localization data to the motion or path planning that calculates the trajectory of the vehicle, in turn performed by the motion execution. If perception generates inaccurate data, the trajectory is going to be flawed. In the worst-case, it leads to catastrophic results.
A successful AD system implementation rests on a state-machine architecture that can formulate a truthful understanding of the environment, produce an efficient motion plan, and flawlessly perform its execution.
To read the full article, click here
Related Semiconductor IP
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
- Verification IP for eUSB 2 v2 and USB 2.0
- AFDX 1G Switch IP
Related Articles
- Basics of SoC I/O design: Part 2 - Hot swap & other implementation issues
- Why FIR sensing technology is essential for achieving fully autonomous vehicles
- Key Safety Design Overview in AI-driven Autonomous Vehicles
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing