Using a PCIe over Cabling-based platform to create hybrid FPGA/virtual platform prototypes
Troy Scott, Synopsys
Embedded.com (May 21, 2013)
FPGA-based prototypes deliver high value to a SoC development organization by providing multi-megahertz processing performance, real world I/O connectivity, and portability for distribution to software developers or field testing scenarios. The prototypes deliver operational systems running fast enough to make embedded software development and hardware/software validation feasible. Teams that have adopted FPGA-based prototyping realize months in shortened schedules and a more efficient and parallel hardware/software engineering methodology.
To fully realize the potential of these systems and maximize the return on investment from prototyping systems, development teams are taking advantage of advanced data exchange links beyond traditional JTAG. High-bandwidth physical links like PCI Express (PCIe) over Cabling allow the prototype to communicate with custom user applications for system control and monitoring. With a transaction-level interface to a SystemC/TLM virtual prototype, a new class of hybrid prototype is possible that leverages the strengths of both hardware and software-based prototyping methods.
To read the full article, click here
Related Semiconductor IP
- PCIe - PCI Express Controller
- Scalable Switch Intel® FPGA IP for PCI Express
- Multichannel DMA Intel FPGA IP for PCI Express*
- PCI Express Gen5 SERDES PHY on Samsung 8LPP
- PCI Express Gen4 SERDES PHY on Samsung 7LPP
Related Articles
- Enabling Composable Platforms with On-Chip PCIe Switching, PCIe-over-Cable
- Pondering the SoC platform
- Panel finds many ways to build a platform
- MEMS market to grow 75-87% over five-year period, says report
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing