How to verify control loop design
Steve Sandler, Analytical Engineering, Inc.
EDN (October 30, 2013)
The non-invasive stability assessment is a method that uses an output impedance measurement to accurately determine stability without access to the control loop. The non-invasive stability assessment, whether performed as a physical test or with a circuit simulation, is a fast, simple, and inexpensive means to verify or optimize any control loop design. This measurement is useful in almost all systems, though especially in high-speed, instrumentation, and RF systems. Improving stability reduces noise in a system, allowing better SNR, dynamic range, clock jitter and many other performance characteristics to be enhanced. Issues related to noise can be very difficult to trace and fix. Non-invasive testing is sometimes the only way to single out and eliminate potential stability problems.
As discussed in reference 1, the non-invasive stability assessment involves measuring the output impedance at the output of the regulator or switching converter. The phase margin is then determined mathematically from the characteristics of the output impedance. Following are four items you should know about the non-invasive phase margin measurement.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- How to Verify Complex RISC-V-based Designs
- How to manage changing IP in an evolving SoC design
- How to Elevate RRAM and MRAM Design Experience to the Next Level
- How to Design Secure SoCs: Essential Security Features for Digital Designers
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM