How to use FPGAs to implement high-speed RLDRAM II interfaces
By Sanjay Charagulla, Altera
August 30, 2006, pldesignline.com
RLDRAM II devices bridge the gap between DDR SDRAM and SRAM; FPGAs offer a solution that enables FPGA-to-RLDRAM II interface performance to run up to 300 MHz.
Increasing I/O bandwidth requirements in the graphics, telecom, and communication industries and growing PC processor speeds are fueling a need for high performance memory interfaces. This "How To" article focuses on RLDRAM II technology and the implementation of a high-speed interface in programmable logic. Techniques are identified that a programmable logic memory controller designer should implement to overcome these barriers. In particular, a case is presented for using embedded silicon approaches in programmable logic for automatic alignment of data strobes to data during the READ and WRITE cycles.
The market need for RLDRAM II
To keep up with the growing industry needs, system designers migrated from single data rate (SDR) SDRAM memory to double data rate (DDR) SDRAM and further to DDR2 SDRAM memory devices. Memory access latency, however, has become a huge bottleneck for communication and networking applications. Reduced Latency DRAM I (RLDRAM I) has evolved to fulfill requirements of these applications. Reduced Latency DRAM II (RLDRAM II) memory combines the networking and cache required by applications such as high density (256Mb), high bandwidth (2.4Gbps), and fast SRAM-like random access times.
RLDRAM II interface overview
RLDRAM II uses a DDR scheme, performing two data transfers per clock. RLDRAM II devices use either the 1.5V HSTL or 1.8V HSTL class I/II I/O standards. Each RLDRAM II device is divided into eight banks, where each bank has a fixed number of rows and columns. WRITE and READ operations are burst oriented and all the bus width configurations of RLDRAM II support burst lengths of 2, 4, and 8 bits. In addition, RLDRAM II devices support bus width configurations of ×9, ×18, and ×36.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- How to use snakes to speed up software without slowing down the time-to-market?
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
- How to design secure SoCs, Part II: Key Management
- How to create energy-efficient IIoT sensor nodes
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace