How to lower the cost of PCI Express adoption by using FPGAs
By Abhijit Athavale, Xilinx
This "How To" article shows how FPGAs are driving the adoption of PCI Express in the embedded market.
As the industry transitions from traditional, bus-based shared I/O schemes with system synchronous clocking (such as PCI), point-to-point system interconnects that use serial I/O technologies are fast becoming the norm. While PCI has been the most widely used bus standard in the PC, server and embedded market for the past decade, PCI Express – with its wide appeal across industry segments – is widely seen as the future of PCI. In fact, it is estimated that PCI Express will replace 80% of all existing PCI ports by the end of 2007 (Fig 1).
This "How To" article shows how FPGAs are driving the adoption of PCI Express in the embedded market.
As the industry transitions from traditional, bus-based shared I/O schemes with system synchronous clocking (such as PCI), point-to-point system interconnects that use serial I/O technologies are fast becoming the norm. While PCI has been the most widely used bus standard in the PC, server and embedded market for the past decade, PCI Express – with its wide appeal across industry segments – is widely seen as the future of PCI. In fact, it is estimated that PCI Express will replace 80% of all existing PCI ports by the end of 2007 (Fig 1).
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