How to design and verify mixed-signal FPGAs
A 'smart' system design and verification flow for mixed-signal FPGAs helps digital designers overcome the complexities of the analog domain.
By Michael Mertz and Venkatesh Narayanan, Actel
October 04, 2006 -- pldesignline.com
In order to meet the market's increasing demands for higher-performance functionality, smaller system form factors, and the reduction of cost and power, system designers are integrating higher levels of mixed-signal functionality into their system-on-chip (SoC) designs.
As the number of mixed-signal components in these SoC designs increases, basic functional verification becomes critical for early silicon success. Without this, system designers will spend millions of dollars on silicon re-spins, waste precious design and verification resources and quite possibly miss their market window.
Luckily, system designers today have more choices than in the past. It is no longer necessary when designing a mixed-signal system to be limited to mixed-signal ASICs, analog MCUs or discrete components. Mixed-signal FPGAs add a new dimension to the system integration puzzle, improving aspects of system integration, such as total system cost, reliability, reconfigurability, time to market, etc. At its core, this new paradigm – the "programmable system chip" (PSC) – integrates FPGA gates, embedded flash and analog functionality into a single programmable device, offering an ideal low cost path with true programmability, and with which system designers can rapidly design and develop their complex mixed-signal systems.
By Michael Mertz and Venkatesh Narayanan, Actel
October 04, 2006 -- pldesignline.com
In order to meet the market's increasing demands for higher-performance functionality, smaller system form factors, and the reduction of cost and power, system designers are integrating higher levels of mixed-signal functionality into their system-on-chip (SoC) designs.
As the number of mixed-signal components in these SoC designs increases, basic functional verification becomes critical for early silicon success. Without this, system designers will spend millions of dollars on silicon re-spins, waste precious design and verification resources and quite possibly miss their market window.
Luckily, system designers today have more choices than in the past. It is no longer necessary when designing a mixed-signal system to be limited to mixed-signal ASICs, analog MCUs or discrete components. Mixed-signal FPGAs add a new dimension to the system integration puzzle, improving aspects of system integration, such as total system cost, reliability, reconfigurability, time to market, etc. At its core, this new paradigm – the "programmable system chip" (PSC) – integrates FPGA gates, embedded flash and analog functionality into a single programmable device, offering an ideal low cost path with true programmability, and with which system designers can rapidly design and develop their complex mixed-signal systems.
To read the full article, click here
Related Semiconductor IP
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
Related Articles
- How to Elevate RRAM and MRAM Design Experience to the Next Level
- How to design secure SoCs, Part V: Data Protection and Encryption
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
- How to Verify Complex RISC-V-based Designs
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety