How to design 65nm FPGA DDR2 memory interfaces for signal integrity
By David Banas, Xilinx
January 24, 2007 -- pldesignline.com
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a Signal Integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives.
January 24, 2007 -- pldesignline.com
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
This article presents practical techniques for incorporating "correctness by design" in DDR2 interfaces, from a Signal Integrity (SI) perspective, using the current generation of available design tools. Some common DDR2 design errors are analyzed, as well as the tradeoffs between some popular design alternatives.
To read the full article, click here
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