How NXP uses Spirit/ESL-based IP ''Yellow Pages'' to speed System-on-Chip design time
By Ralph von Vignau, NXP Semiconductors
Dec 6 2006 (0:30 AM), Embedded.com
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.
Forget the hand-crafting. In today's fast-moving consumer electronics industry, achieving short time-to- market is the single most effective way of maximizing semiconductor sales and profit. The chances are you will still be able to push the SoC down the price curve by migrating it to a next generation CMOS process technology within 18 months or so.
In addition to providing cost down on existing designs, each new CMOS process is going to allow the design of ever more complex chips. Reducing time-to- market for these new designs will therefore require you to manage an ever-increasing level of complexity in a way that cuts both design and verification times.
Dec 6 2006 (0:30 AM), Embedded.com
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.
Forget the hand-crafting. In today's fast-moving consumer electronics industry, achieving short time-to- market is the single most effective way of maximizing semiconductor sales and profit. The chances are you will still be able to push the SoC down the price curve by migrating it to a next generation CMOS process technology within 18 months or so.
In addition to providing cost down on existing designs, each new CMOS process is going to allow the design of ever more complex chips. Reducing time-to- market for these new designs will therefore require you to manage an ever-increasing level of complexity in a way that cuts both design and verification times.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- How to manage changing IP in an evolving SoC design
- How to use snakes to speed up software without slowing down the time-to-market?
- ESL Methods for Optimizing a Multi-media Phone Chip
- A 24 Processors System on Chip FPGA Design with Network on Chip
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM