How flash-based FPGAs simplify functional safety requirements
Ted Marena, Microsemi
embedded.com (June 19, 2018)
As the quantity of industrial equipment controlled by electronics grows, so do concerns over the equipment failing and causing personal harm and property damage. Safety functions are built into equipment to prevent functional failure and ensure that if a system does fail, it fails in a nonharmful way. Examples of safety systems in industrial equipment include train breaks, sensors monitoring hazards to air quality or the physical environment, assembly line assistance robots, and distributed control in process automation equipment, just to name a few. These systems often include field programmable gate arrays (FPGAs) that, when supported by safety data packages for calculating failure rates, can play a pivotal role in streamlining safety assessments. When these devices are also flash-based and therefore immune to single event upsets (SEUs), FPGAs enable safety system developers to dramatically simplify their designs.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- FPGAs & Functional Safety in Industrial Applications
- How NoCs ace power management and functional safety in SoCs
- CAST Provides a Functional Safety RISC-V Processor IP for Microchip FPGAs
- How to use FPGAs to develop an intelligent solar tracking system
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs