High-definition video scaler ASIC development from FPGA
By Wolfgang Hoeflich, Senior Field Applications Engineer, AMI Semiconductor
videsignline.com, September 29, 2006
How a high-definition video scaler ASIC was quickly created using a flexible FPGA-to-ASIC conversion flow. This ensured reproduction of the FPGA functionality and enabled first time fully functional silicon supporting video resolutions up to 1080p.
Consumers are buying ever larger numbers of liquid crystal displays (LCD), plasma and digital light processing (DLP) based systems. As digital displays continue to offer higher resolution capabilities, high quality video scaling is becoming a key feature for the new generation of high definition video sources.
This article details the implementation and verification flows of a high-definition video scaler ASIC implemented in a 0.18um standard cell technology. The Anchor Bay Technology application targets the consumer market space for high-definition video sources (for example, HD-DVD and Blu-ray players). Achieving quick time-to-market was critical for the success of the project, in addition to beating competitive products in cost, features and ease-of-use. An FPGA prototype was used for at-speed verification of all functionality, especially image quality enhancements.
videsignline.com, September 29, 2006
How a high-definition video scaler ASIC was quickly created using a flexible FPGA-to-ASIC conversion flow. This ensured reproduction of the FPGA functionality and enabled first time fully functional silicon supporting video resolutions up to 1080p.
Consumers are buying ever larger numbers of liquid crystal displays (LCD), plasma and digital light processing (DLP) based systems. As digital displays continue to offer higher resolution capabilities, high quality video scaling is becoming a key feature for the new generation of high definition video sources.
This article details the implementation and verification flows of a high-definition video scaler ASIC implemented in a 0.18um standard cell technology. The Anchor Bay Technology application targets the consumer market space for high-definition video sources (for example, HD-DVD and Blu-ray players). Achieving quick time-to-market was critical for the success of the project, in addition to beating competitive products in cost, features and ease-of-use. An FPGA prototype was used for at-speed verification of all functionality, especially image quality enhancements.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Generating High Speed CSI2 Video by an FPGA
- Micros benefit from ASIC heritage
- Meeting the Challenge of Real-Time Video Encoding: Migrating From H.263 to H.264
- Processor Architecture for High Performance Video Decode
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs