Reducing Turnaround Time with Hierarchical Timing Analysis
Sunil Walia, Synopsys
EETimes (10/3/2011 10:32 AM EDT)
The semiconductor industry accepts two facts: designs continue to grow in size and complexity, and time-to-market pressure is higher than ever. I’ll use the ‘smart phone’ as an example to make my point. On a smart phone you can now talk, text, IM, take pictures and videos, play games and perform a host of other tasks. Question: How is this possible? Answer: By integrating multiple functionalities capable of simultaneous interaction onto a single chip. Question: How do you make this happen within the same amount of time you are given as the last chip? Answer: Design reuse.
As design evolution continues, packing lots more on a single die, ‘design reuse’ has become a common technique. There is reuse of IPs, flows, and methodologies – all causing the design size growth to sometimes surpass Moore’s Law. However, designers are feeling the squeeze between packing tons of functionality on one end and experiencing no relaxation in time-to-market requirements at the other. Market dynamics dictate that if you snooze, you lose.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- Cell model creation for statistical timing analysis
- Practical Applications of Statistical Static Timing Analysis
- Removing pessimism and optimism in timing analysis
- Static timing analysis: bridging the gap between simulation and silicon
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow